Call for Papers - ASP-DAC 2026

The 31st Asia and South Pacific Design Automation Conference (ASP-DAC 2026) is the premier international forum for the discussion of the state-of-the-art and future trends in the field of VLSI design and design automation.

ASP-DAC 2026 will be held from January 19-22, 2026, at the Hong Kong Disneyland Hotel.

Aims of the Conference

ASP-DAC 2026 is the 31st annual international conference on VLSI design automation in Asia and South Pacific regions, one of the most active regions of design, CAD, and fabrication of silicon chips in the world. The conference aims to provide the Asian and South Pacific CAD/DA and Design community with opportunities to present recent advances and with forums for future directions in technologies related to design and Electronic Design Automation (EDA). The format of the meeting intends to cultivate and promote an instructive and productive interchange of ideas among EDA researchers/developers and system/circuit/device designers. All scientists, engineers, and students who are interested in theoretical and practical aspects of VLSI design and design automation are welcomed to ASP-DAC.

ASP-DAC recognizes excellent contributions with the Best Paper Award and 10-Year Retrospective Most Influential Paper Award.

Areas of Interest

Original papers in, but not limited to, the following areas are invited:

1. System-Level Modeling and Design Methodology
   1.1 HW/SW co-design, co-simulation and co-verification
   1.2 System-level design exploration, synthesis, and optimization
   1.3 System-level formal verification
   1.4 System-level modeling, simulation and validation
   1.5 Networks-on-chip and NoC-based system design

2. Embedded, Cyberphysical (CPS), IoT Systems, and Software
   2.1 Many- and multi-core SoC architecture
   2.2 IP/platform-based SoC design
   2.3 Real-time systems/Dependable architecture
   2.4 Cyber-physical systems and Internet of Things
   2.5 Kernel, middleware, and virtual machine
   2.6 Compiler and toolchain
   2.7 Resource allocation for heterogeneous computing platform
   2.8 Storage software and application

3. Memory Architecture and Near/In-Memory Computing
   3.1 Storage system and memory architecture
   3.2 On-chip memory architectures and management: Scratchpads, compiler, controlled memories, etc.
   3.3 Memory/storage hierarchies and management for emerging memory technologies
   3.4 Near-memory and in-memory computing

4. Tools and Methods for Building Artificial Intelligence (AI)
   4.1 Design methods for learning on a chip
   4.2 Tools and design methodologies for edge AI and TinyML
   4.3 Efficient ML training and inference
   Note: papers on AI/LLM-assisted tools and design methods should be submitted to respective tracks.

5. Hardware Systems and Architectures for AI
   5.1 Hardware, device, architecture, and system-level design for deep neural networks
   5.2 Hardware acceleration for LLM
   5.3 Neural network acceleration co-design techniques
   5.4 Novel reconfigurable architectures, including FPGAs for AI/MLs

6. Photonic/RF/Analog-Mixed Signal Design
   6.1 Photonic/RF/Analog-mixed signal synthesis, layout, and verification
   6.2 High-frequency electromagnetic and circuit simulations
   6.3 Mixed-signal design consideration
   6.4 Communication and computing using photonics

7. Approximate, Bio-Inspired and Neuromorphic Computing
   7.1 Circuit and system techniques for approximate, hyper-dimensional, and stochastic computing
   7.2 Neuromorphic computing
   7.3 CAD for approximate and stochastic systems
   7.4 CAD for bio-inspired and neuromorphic systems

8. High-Level, Behavioral, and Logic Synthesis and Optimization
   8.1 High-level/Behavioral synthesis tool and methodology
   8.2 Combinational, sequential, and asynchronous logic synthesis
   8.3 Synthesis for deep neural networks
   8.4 Technology mapping, resource scheduling, allocation, and synthesis
   8.5 Functional, logic, and timing ECO (engineering change order)
   8.6 Interaction between logic synthesis and physical design

9. Physical Design and Timing Analysis
   9.1 Floorplanning, partitioning, placement, and routing optimization
   9.2 Interconnect planning and synthesis
   9.3 Clock network synthesis
   9.4 Post-layout and post-silicon optimization
   9.5 Package/PCB/3D-IC placement and routing
   9.6 Extraction, TSV, and package modeling
   9.7 Deterministic/statistical timing analysis and optimization

10. Design for Manufacturability/Reliability and Low Power
    10.1 Reticle enhancement, lithography-related design, and optimization
    10.2 Design for manufacturability, yield, and defect tolerance
    10.3 Reliability, robustness, aging, and soft error analysis
    10.4 Power modeling, analysis, and simulation
    10.5 Low-power design and optimization at circuit and system levels
    10.6 Thermal-aware design and dynamic thermal management
    10.7 Energy harvesting and battery management
    10.8 Signal/Power integrity, EM modeling and analysis

11. Testing, Validation, Simulation, and Verification
    11.1 ATPG, BIST, and DFT
    11.2 System test and 3D IC test, online test, and fault tolerance
    11.3 Memory test and repair
    11.4 RTL and gate-leveling modeling, simulation, and verification
    11.5 Circuit-level formal verification
    11.6 Device/circuit-level simulation tool and methodology

12. Hardware and Embedded Security
    12.1 Hardware-based security
    12.2 Detection and prevention of hardware trojans
    12.3 Side-channel attacks, fault attacks, and countermeasures
    12.4 Design and CAD for security
    12.5 Cyberphysical system security
    12.6 Nanoelectronic security
    12.7 Supply chain security and anti-counterfeiting
    12.8 Security/privacy for LLM/AI/ML

13. Emerging Devices, Technologies and Applications
    13.1 EDA and circuits design for quantum and Ising computing
    13.2 Nanotechnology, MEMS
    13.3 Biomedical, biochip, and biodata processing
    13.4 Edge, fog, and cloud computing
    13.5 Automotive and smart-energy systems design and optimization
    13.6 New device and process technologies

Submission Guidelines

• Authors must submit full-length, double-columned, original papers, with a maximum of 6 pages in PDF format (including the abstract, figures and tables).
• One page of references is allowed, which does not count towards the 6-page limitation.
• ASP-DAC does not allow double and/or parallel submissions of similar work to any other conferences, symposia, or journals. Extended abstracts published elsewhere may be submitted but must include sufficient new content.
• The submission must not include information that serves to identify the authors of the manuscript, such as name(s) or affiliation(s) of the author(s), anywhere in the manuscript, abstract, references, and bibliographic citations.
• While research papers with open-source software are highly encouraged where the software will be made publicly available (via GitHub or similar), the authors’ identities need to be anonymized in the submitted paper for the double-blind review process.
• Issuing the paper as a technical report, posting the paper on a website, or presenting the paper at a workshop that does not publish formally reviewed proceedings does not disqualify it from appearing in the proceedings.
• Each paper shall be accompanied by at least one different conference registration at the speaker’s registration rate.
• ACM and IEEE reserve the right to exclude a paper from distribution after the conference (e.g., removal from ACM Digital Library and IEEE Xplore) if the paper is not presented at the conference by any author.

Submission of Papers

• Deadline for Abstract submission: July 4 (Fri), 2025, 5 PM AOE (Anywhere on earth)
• Deadline for PDF uploading: July 11 (Fri), 2025, 5 PM AOE (Anywhere on earth)
• Announcement of accepted manuscript IDs: September 2 (Tue), 2025
• Notification of acceptance: September 5 (Fri), 2025
• Deadline for final version: October 31 (Fri), 2025, 5 PM AOE (Anywhere on earth)

For detailed instructions for submission, please refer to the “Authors’ Guide” at: https://www.aspdac.com/aspdac2026/author

Paper submission site: https://easychair.org/conferences/?conf=aspdac2026

ASP-DAC 2026 Chairs

• General Chair: Tsung-Yi Ho (The Chinese University of Hong Kong)
• Technical Program Chair(s): Takashi Sato (Kyoto University)
• Technical Program Vice Chair(s): Seokhyeong Kang (Pohang University of Science and Technology)

Panels, Special Sessions and Tutorials

Suggestions and proposals are welcome and have to be addressed to:

• aspdac2026-ss@aspdac.com for special sessions & panels
• aspdac2026-tutorial@aspdac.com for tutorials

Proposals must be submitted no later than September 8 (Mon), 2025.

Contact

• Conference Secretariat: aspdac2026 [at] aspdac.com
• TPC Secretariat: aspdac2026-tpc [at] aspdac.com