Call for Papers: ICCD 2025

The 43rd IEEE International Conference on Computer Design (ICCD 2025) invites submissions for original research in the design and implementation of computer systems and their components. The conference will be held in Dallas, USA, from November 10-12, 2025.

Topics of Interest

ICCD encompasses a wide range of topics, with a focus on future systems and technologies. The conference is structured into the following tracks:

• Track 1. Computing Systems: System architecture; System support for multi/many cores, co-processors, and accelerators; System support for security, reliability, and energy efficiency and proportionality; Virtual memory; System support for emerging technologies, including NVM, quantum, neuromorphic, bio-inspired computing, machine learning and artificial intelligence applications; Storage systems for data center and cloud/edge computing, high-performance computing (HPC), exascale system, and serverless computing.
• Track 2. Software Architectures, Compilers, and Tool Chains: Software architectures, compilers, programming language/model, firmware, OS, hypervisor, runtime design, and co-design for embedded/real-time systems; Middleware for embedded systems, including resource-awareness, reconfiguration, energy/power management; compiler support for enhanced debugging, profiling, and traceability.
• Track 3. Hardware Architectures: Microarchitecture design techniques for single-threaded and multi/many-core processors, such as instruction-level parallelism, pipelining, caches, branch prediction, multithreading, and networks-on-chip; Techniques for low-power, secure, and reliable processor architectures; Hardware acceleration for emerging applications including NVM, quantum, neuromorphic, bio-inspired; Hardware support for processor virtualization; Real-life design challenges: case studies, tradeoffs, retrospectives.
• Track 4. Test, Verification, and Security: Design error debug and diagnosis; Fault modeling; Fault simulation and ATPG; Analog/RF testing; Statistical test methods; Large volume yield analysis and learning; Fault tolerance; DFT and BIST; Functional, transaction-level, RTL, and gate-level modeling and verification of hardware designs; Equivalence checking, property checking, and theorem proving; Constrained-random test generation; High-level design and SoC validation; Hardware security primitives and methodologies; Side-channel analysis, attacks and mitigations for processors and accelerators; Interaction between test, security and trust.
• Track 5. Electronic Design Automation: System-level design and synthesis; High-level, logic, and physical synthesis; Analysis and optimization of timing, power, variability/yield, temperature, and noise; Physical design, including partitioning, floorplanning, placement, and routing; Clock tree synthesis; Verification methods at different levels of the EDA flow; Tools for multiple-clock domains, asynchronous, and mixed-timing methodologies; CAD support for accelerators, FPGAs, SoCs, ASICs, NoC, and general-purpose processors; CAD for manufacturing, test, verification, and security; Tools and design methods for emerging technologies (photonics, MEMS, spintronics, nano, quantum); interaction of EDA and AI/ML.
• Track 6. Logic and Circuit Design: Circuit design techniques for digital, memory, analog, and mixed-signal systems; Circuit design techniques for high performance and low power; Circuit design techniques for robustness under process variability, electromigration, and radiation; Design techniques for emerging and maturing technologies (MEMS, nano-spintronics, quantum, flexible electronics, multi-gate devices, in-memory computing); Asynchronous circuit design; Signal-processing, graphic-processor, and datapath circuits.

Important Dates

• Notification of Acceptance: August 01, 2025

Submission Guidelines

• Papers should be formatted according to the IEEE conference paper guidelines using the letter page size and a 10-pt font size.
• Submissions are double-blind; all information identifying authors should be removed.
• In the submission stage, paper size is limited to 8 pages, including figures, references, and appendix.
• All papers will be evaluated with regard to their suitability for the conference, originality and technical soundness.
• The program committee reserves the right to accept a submission as a short 4 pages paper.
• Each accepted paper must be accompanied by a unique full registration to be included in the program.
• Each accepted paper must be presented by one of the authors in person at the conference to be included in the published proceedings.
• The list of authors, paper title, and abstract must be registered in the Easychair system by the abstract submission deadline.
• The full paper must be submitted by the paper submission deadline.

Contact

Any questions about submission should be directed to the Program Chairs, Fei Yao and Wei Zhang. Please consult the ICCD 2025 website for additional information about the conference and submission details.